1. Field of the Invention
The present invention relates generally to memory systems and, an in particular, to a memory system having the capability of addressing to access any particular byte of data at any location in the memory or any unit of data comprising multiple bytes of data.
2. Description of the Related Art
Semiconductor memory systems are available having a substantial storage capacity. Such systems include non-volatile memory systems which have the capability of emulating mass magnetic storage devices such as hard disk drives. Such drives have a relatively slow access speeds as compared to semiconductor memories when a single byte of data is to be read or programmed. However, when multiple sequential bytes are to be read or programmed, the access speed of hard disk drives approaches that of certain types of non-volatile memories such as flash memory systems.
In many semiconductor memory applications, such as systems which emulate hard disk drives, it would be desirable to have the capability of both efficiently accessing a single byte of data in a random access fashion and efficiently accessing a unit of data comprising multiple bytes of data. The present invention is directed to a memory system which provides this capability and possesses other advantages as will be apparent to those skilled in the art upon a reading of the following Detailed Description of the Preferred Embodiment together with drawings.
Data systems incorporating memory systems having multiple memory devices are well known. By way of example, FIG. 1 depicts a simplified conventional memory system which includes a host device 20, an address decoder 22 and memory devices 24A and 24. The host device 22 may be a microprocessor and the memory devices 24A and 24B may be separate memory integrated circuits. An address bus 26 is used to provide addresses to an address decoder 22 and to the memory devices 24A and 24B. The address decoder 22 has two outputs connected to enable inputs of the memory devices 24A and 24B. Typically, the most significant bit(s) of the address are provided on the bus 26 to the decoder 22, with the remaining address bits being provided to each of the memory devices.
When memory is to be accessed, the processor 20 causes the address decoder 2 to decode the most significant bit(s) of the memory address placed on an address bus 26. The decoder 22 will select one of the two memory devices 24A and 24B by generating either signal Sel 0 or Sel 1. The selected memory device will respond to the address presented to it on the address bus and the deselected memory device, which is disabled, will not respond. Although not shown, a data bus is used to transfer data between the memory devices and the processor 20, with only the selected device outputting data to the data bus during memory read operations.
The approach depicted in FIG. 1 is sometimes referred to as radial device selection where each memory device has a separate select input. This approach works well when relatively few memory devices are employed and where access speed, particularly random access speed, is important. However, if a large number of memory devices are used so that large amounts of data can be stored, the requirement of separate select lines for each memory device results in large memory boards and a relatively large pin count for the control logic circuitry. Thus, unless access speed is critical and a large number of memory devices are used, the radial device selection approach of FIG. 1 is not ideal.
FIG. 2 shows an alternative prior art device selection technique, sometimes referred to as serial selection. Again, a host device 28 is used which is connected to several memory devices 30A, 30B and 30C by way of a system bus 32. The memory devices 30A, 30B and 30C are usually implemented as separate integrated circuits. The system bus 32 includes memory address and memory data and various control signals so that each of the memory devices 30A, 30B 30C receives the same addresses, data and other signals. Each memory device is preassigned a unique address so that only one device will be accessed by the host device 28 during a memory operation. Typically, the memory devices 30A, 30B and 30C are assigned addresses by way of jumper or switch settings represented by elements 34A, 34B and 34C.
The FIG. 2 approach also requires that dedicated pins be provided on each of the integrated circuit memory devices 30A, 30B and 30C to receive the jumper wires or switches for assigning the addresses. These pins increase the pin count for the integrated circuits thereby increasing the cost of the packaging for the devices and increasing the likelihood that there will be mechanical problems and manufacturing errors through soldering and the like. These extra pins are also subject to defects and increase the possibility of damage to the integrated circuits as a result of electrostatic discharge.
A memory system comprising a-memory controller, an array of non-volatile memory cells and a memory operation manager is disclosed, with the array and operation manager preferably being implemented in an integrated circuit separate from the memory controller. The memory controller is configured to issue memory program instructions, memory read instructions and memory erase instructions to the memory operation manager, preferably over a system bus. The program instructions include program data information and program address information.
The memory operation manager is configured to carry out the memory program operations in response to receipt of one of the memory program instructions, memory read operations in response to receipt of one of the memory read instructions and memory erase operations in response to one of the memory erase instructions. The operation manager further comprises a memory address block configured to control memory addresses used in memory read and program operations. The memory address block contains a memory address derived from the read address information used during memory read operations and a memory address derived from the program address information used during memory program operations.
The memory address in the memory address block has a most significant address portion and a least significant address portion. The least significant address portion of the memory block may be implemented, by way of example, in the form of a counter having an associated circuitry for enabling and disabling a counter increment function. The memory address block is configured to modify the least significant address portion, with the modification being independent of the program address and read address information. The memory operations manager further comprises a memory data block configured to control data used in the memory program operations.
In a typical memory read operation, it is possible to read multiple addresses of the array using a limited number of memory read instructions. Similarly, in a typical memory program operation, it is possible to program multiple addresses using a limited number of memory program instructions. By way of example, the memory controller can be implemented to provide an initial address for the memory operation and an instruction which permits the memory operation manager to generate subsequent addresses used in the memory operation thereby eliminating the need for the memory controller to transfer a large number of addresses to the memory operation manager.